A technology has been reported, in which, in a solid-state image-pickup device, for example, a CMOS image sensor in which column-parallel ADCs are mounted, an up/down counter is used in an ADC that compares an analog signal which is output from a unit pixel with a reference voltage, and that converts the analog signal into a digital signal on the basis of the comparison result, thereby facilitating an operation of canceling an offset value of a reset level that is output when the unit pixel is reset (for example, see Japanese Unexamined Patent Application Publication No. 2005-303648).
FIG. 11 is a block diagram showing a configuration of a CMOS image sensor 100, in which column-parallel ADCs are mounted, according to an example of the prior art.
In FIG. 11, unit pixels 101 have photodiodes and in-pixel amplifiers, and are two-dimensionally disposed in a matrix form, thereby configuring a pixel-array section 102. For an n row-m column disposition of pixels in the pixel-array section 12, each of row control lines 103 (103-1 to 103-n) is disposed in a corresponding one of rows, and each of column signal lines 104 (104-1 to 104-m) is disposed in a corresponding one of columns. Control of row addressing or row scanning for the pixel-array section 102 is performed by a row scanning circuit 105 via the row control lines 103-1 to 103-n.
A column processing circuit 106 is disposed for each of the column signal lines 104-1 to 104-m on a side of one end of the one of the column signal lines 104-1 to 104-m. The column processing circuit 106 is configured by having a comparison circuit 107, an up/down counter 108, a transfer switch 109, and a memory circuit 110.
In the column processing circuit 106, the comparison circuit 107 performs the magnitude comparison between an output signal of a corresponding one of the unit pixels 101 of a selected row, which is obtained via a corresponding one of the column signal lines 104-1 to 104-m, and a reference voltage Vref that is generated by a digital-to-analog conversion circuit (hereinafter, abbreviated as DAC (Digital-Analog Converter)) 111. The DAC 111 generates the reference voltage Vref on the basis of a control signal CS1 and a clock CKS that are supplied from the timing control circuit 112 which operates in synchronization with a master clock MCK.
The operation of the up/down counter 108 is controlled by a control signal CS2 that is supplied from the timing control circuit 112. The up/down counter 108 performs up-counting or down-counting in synchronization with the clock CK, and stops counting in accordance with a change in an output Vco of the comparison circuit 107. The transfer switch 109 is controlled by a control signal CS3 that is supplied from the timing control circuit 112 so that the transfer switch 109 is turned on (open)/turned off (closed), and transfers a counter value of the up/down counter 108 to the memory circuit 110. Counter values that are maintained in the memory circuit 110 are sequentially read by column scanning with a column scanning circuit 113 to a horizontal output line 114, and are obtained as image-pickup data.
Next, an operation of the CMOS image sensor 100, which has the above-described configuration, according to the example of the prior art will be described with reference to a timing chart shown in FIG. 12.
A reset component ΔV of the unit pixel 101 is read in a first reading operation. The reset component ΔV includes, as an offset, noise that has a fixed pattern and that varies among the unit pixels 101. However, because the variation of the reset component ΔV is generally small and the reset level is common for all of the pixels, signal voltages Vx of the column signal lines 104-1 to 104-m are approximately known.
Accordingly, in a case of the first reading of the reset component ΔV, a comparison period in the comparison circuit 107 can be reduced by adjusting the reference voltage Vref. Regarding reading of the reset component ΔV, the up/down counter 108 performs down-counting in synchronization with the clock CK, and continues counting until the output Vco of the comparison circuit 107 changes. A counter value in a case in which the output Vco of the comparison circuit changes and in which counting stops corresponds to ΔV.
Although a signal component Vsig of the unit pixel 101 is read in a second reading, in addition to the signal component Vsig, a variation component ΔV is included in a read value in this case. In the second reading, the up/down counter 108 performs up-counting in synchronization with the clock CK, and continues counting until the output Vco of the comparison circuit 107 changes.
Because a counter value that is obtained by up-counting corresponds to the sum of the signal component Vsig and the variation component ΔV, a value that is obtained by subtracting a result of the first reading from a result of the second reading corresponds the signal component Vsig. In other words, a value that is obtained by up-counting from an initial counter value which is provided before the first reading is performed corresponds to the signal component Vsig. This corresponds to an operation of correlated double sample (CDS) in which a variation component is cancelled.
In the CMOS image sensor 100 in which column-parallel ADCs are mounted, it is desired that the resolution of AD conversion be high. In contrast, in a unit pixel having a large amount of incident light, random noise caused by shot noise is predominant, and the necessity to perform high-resolution AD conversion is not great. High-resolution AD conversion is particularly required for a case in which the amount of incident light is small, and in which the amplitude of the output of the unit pixel 101 is small.
In the above-described CMOS image sensor 100, in which column-parallel ADCs are mounted, according to the example of the prior art, when the resolution of the AD conversion is to be increased, the number of clocks that is necessary for a counting operation of the up/down counter 108 increases. For example, when 10-bit AD conversion is to be performed, 210 clocks (=1024 clocks) are necessary. Furthermore, when 12-bit AD conversion, which is realized by adding two bits to 10 bits, is to be performed, 212 clocks (=4096 clocks) are necessary. In other words, the necessary number of clocks is of the order of the exponent of the resolution, and it was difficult to realize both high-resolution AD conversion and enhancement of the speed of AD conversion.
Hence, the present invention aims to provide a solid-state image-pickup capable of performing high-resolution AD conversion at a high speed, a method for driving the solid-state image-pickup device, and an image-pickup apparatus.